Heat is a critical bottleneck to the performance and reliability of microelectronic circuits and systems. Wide-bandgap GaN and SiC devices operate at much higher power density than traditional Si and GaAs devices and thus they tend to generate more heat. Therefore, existing thermal management solutions designed for Si and GaAs devices are usually not adequate for GaN and SiC chips. GaN devices can generate heat fluxes in excess of 1 kW/cm2 and thus novel, highly efficient micro-cooling systems are necessary in order to enable the use of such devices in actual in-use environments.
As just mentioned heat extraction is a major bottleneck for microelectronic chips and as such it has generated a lot of R&D efforts from multiple companies. Advances in silicon micromachining, micro-molding, material science (compound heat sinks with matched CTE, thermoplastic TIM etc) and material growth (CVD grown carbon nano-tubes and thin film diamond) over the last decade have significantly increased the efficiency and heat extraction ability of micro-cooling systems. However, none of these technologies are adequate for wide band gap semiconductors (GaN and SiC) which generate heat fluxes in excess of 1 kW/cm2 and none simultaneously addresses packaging, interconnection and cooling.
The known prior art includes the following:
1. K-C Chen et al, Thermal management and novel package design of high power light emitting diodes, National Cheng Kung University, Taiwan, Electronic Components and Technology Conference, 2008. These authors present a method for cooling high power light emitting diodes (LED) by doing electroless plating of Cu on the backside of the diode (FIG. 1 of their paper shows a cross section of their propose package). They assert that this design reduces junction temperature by up to 40° C. and thermal resistance by as much as 40%. The authors use conventional wirebonds which are applicable to singulated LED chips with fixed chip sizes and thicknesses but cannot be reasonably used for high frequency components due to their parasitic inductance and thus are not compatible when trying to combine multiple chips of various sizes and substrate thicknesses in close proximity to each other.
2. A. A. Ali et al, “Notebook computer with hybrid diamond heat spreader,” Apple Inc., US Patent Application: US 2008/0298021 A1, filed May 31, 2007. The inventors are disclosing the use of CVD deposited thin film diamond for a heat spreader. The chip is mounted on thin film diamond using a TIM material (solder, thermal grease, phase change epoxy, or thin film metal: Ti/Pt/Au layer). The heat spreader is a thin film diamond, a diamond/copper hybrid, a diamond/aluminum hybrid, an aluminum or copper film. The inventors also show different embodiments of their structure where heat pipes are embedded in the heat sink for increase heat transfer coefficient.
3. R. Feeler et al, Next-generation microchannel coolers, Northrop Grumman, Proceedings of SPIE 2008. The authors present a micro-channel cooler for LED arrays using Low Temperature Co-Fired Ceramic (LTCC) material. They propose a heat sink made out of AN, BeO or CVD diamond under the LED chip and then connect this to the LTCC micro-channel. The CTE of LTCC is close to GaAs and InP so the authors are using hard solder (AuSn) to mount the LED on the cooler.
4. J. Oh et al, “Package-on-package system with heat spreader”, US Published Patent Application: US 2009/0294941, filing date: May 30, 2008. The inventors present a package-on-package system that includes mounting the chip on a base substrate, positioning an interposer over the chip and forming a heat spreader around the chip and the interposer. Their approach focuses on multi-stacked chips and extracting heat from inside the stack by inserting the heat spreader between the packages as well as at the top of the module.
5. M. J. Schaenzer et al, Thermally coupling an integrated heat spreader to a heat sink, US Patent Application: US 2006/0027635, filing date: Aug. 9, 2004. The inventors present a mounting method where the base of the heat sink is selectively plated with solder and connected to a heat spreader plated with Au. The heat sink is connected to the top of the chip.
6. CREE Inc. CREE has patent applications related to cooling of semiconductor chips which are identified here by their publication numbers: US 2009/0134421 by G. H. Negley, “Solid metal block semiconductor light emitting device mounting substrates and packages”; US 2008/0099770 by N. W. Mendendorp, “Integrated heat spreaders for light emitting devices and related assemblies”; US 2007/0247851 by R. G. Villard, “Light emitting diode lighting package with improved heat sink”; and US 2006/0292747 by B. P. Loh, “Tops surface mount power light emitter with integral heat sink”.
All these are more traditional cooling approaches and rely on mounting the LED chips on various heat sinks. Our disclosed concept of directly forming the heat sink on the backside of the chips is superior since it offers optimum heat rejection, minimum weight and size, ability to integrate with chips of different size and thickness, and ability to interconnect the chips (especially as this relates to high frequency applications).
7. B. D. Raymond, “Wafer scale integrated thermal heat spreader”, M/A-COM Inc, US Patent Application: US 2009/0108437, filing date: Oct. 29, 2007. This invention of Raymond discloses a method of creating a heat sink by backside metallization of a wafer. This metallization is realized with composite electroplating of various metallic compounds with variable CTE. Some examples are Cu-Diamond, Cr-Diamond, or metallic compounds with Be, BeO and carbon nano-tubes. After the wafer is backside metalized, the individual chips are diced.
8. S. Z. Zhao et al, “Flip chip package including a non-planar heat spreader and method of making the same”, Broadcom Inc, US Patent Application: US 2006/0091509, filing Date Nov. 3, 2004. Zhao et al. discloses a traditional cooling approach focusing on flip-chip interconnected packages. The main concept is the formation of a cavity on the heat sink which allows for easier integration of the chip.
9. Intel: (a) US 2008/0128897 by T. W. Chao, “Heat spreader for a multi-chip package”, which is similar to prior art above, this is a more conventional approach focusing on flip-chip mounted chips. The arguments from the above paragraph are applicable in this case as well; and (b) US 2007/0075420 by D. Lu et al, “Microelectronic package having direct contact heat spreader and method of manufacturing same.” This approach is similar to the D. B. Raymond technique mentioned above.
In summary, the available solutions today are included in the following list. It is believed that none of these approaches can adequately handle the +1 kW/cm2 heat flux with the exception of the forced water-cooled microchannels developed by IBM. However, that approach relies on an expensive external pump to move the water at high flow rates close to the chip. The estimated cost of this approach makes impractical for mass production. Furthermore, none of these solutions adequately addresses the issue of interconnecting these devices which is particularly critical in high frequency applications.
By reviewing the prior art, the disclosed invention offers significant improvements that are not obvious to an a person in this field. For example, this invention addresses the very important issue of interconnecting the packaged devices. Due to the disclosed sequence of the fabrication steps, the present approach offers an excellent solution for simultaneously cooling, packaging and interconnecting microelectronic chips (known-good-die) of various sizes, substrate thicknesses and substrate types (Si, SiGe, SiC, GaAs, GaN, InP, quartz, sapphire or any other suitable microelectronic substrate). Prior art only addresses the cooling problem and does not offer any solutions for overall packaging and interconnecting of the devices.
Interconnection becomes particularly important for high frequency systems where long wirebonds are prohibitive due to their parasitic inductances. However, by using the disclosed 3D interconnection approach with through substrate vias we can achieve excellent interconnection between chips and satisfy a long-felt need of offering a complete system-in-package solution that combines multi-functionality and excellent high frequency performance, encapsulation/packaging and cooling.
This invention is compatible with 3D multi-chip integration which is a recent trend in microelectronics for both commercial and defense applications due to the reduction is size, weight, form factor and power consumption. There are four main motivations for 3D integration:
(1) Form Factor: reduce size and form factor of system
I (2) Increased Electrical Performance: shorten interconnect length, reduce parasitics, reduce power consumption
(3) Heterogeneous Integration: integrate different functional layers (RF, memory, logic, MEMS, imagers, exotic substrates etc) based on different optimized process nodes
(4) Cost: at some point 3D integration will be cheaper than further shrinking 2D design rules.
The invention allows the realization of 3D integrated systems that include an embedded micro-cooling.
The disclosed invention is compatible with low cost manufacturing large panel tape & reel processes and offers the potential of large commercial success in multiple industries (automotive, aerospace & defense, PC, commercial electronics etc).
By eliminating the need for special materials for mounting the chips on the boards (solder and TIM) this invention eliminates two major high thermal resistance bottlenecks which create significant reliability problems in microelectronics. Furthermore, this invention is enabling the introduction of wide band gap devices (GaN, SiC) into systems since these chips operate at higher power densities and generate more heat compared to conventional Si and GaAs devices.